----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    FREQUENCY_DIVIDER 
-- Module Name:    FREQUENCY_DIVIDER 
-- Project Name:   Timer
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity FREQUENCY_DIVIDER is
	generic(
		sys_clk_fre_value: INTEGER := 50000000;
		div_clk_fre_value: INTEGER := 5000
	);
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	
		o_div_clk: out STD_LOGIC	
	);
end entity FREQUENCY_DIVIDER;

architecture behavior of FREQUENCY_DIVIDER is
	signal r_div_count: STD_LOGIC_VECTOR (31 downto 0);
	signal r_div_clk:STD_LOGIC;
begin
	process(i_sys_rst,i_sys_clk)	
		begin
			if (i_sys_rst = '1') then	
				r_div_count <= x"00000000";
				r_div_clk <= '0';
			elsif (i_sys_clk'event AND i_sys_clk = '1') then	
				if (r_div_count = sys_clk_fre_value/div_clk_fre_value/2-1) then
					r_div_count <=  x"00000000";
					r_div_clk <= NOT r_div_clk; 
				else
					r_div_count <= r_div_count+1;
				end if;
			end if;
	end process;
	o_div_clk <= r_div_clk;
end architecture behavior;
